/************************************************************************ * According to the LLP code comments: * for HP82335 which has a 2k memory-mapped block, the 9914 registers * were mapped onto the last 8 locations in that memory block, offsets * 0x3ff8 - 0x3fff. They were preceded by ccir[0x37f8] and csr[0x800]. * HP documentation INCORRECTLY referred to "ccir[0x37f7]". * * The above is NOT self-consistent, 0x4000 is 16k, not 2k, and LLP does * not cite which HP documentation Clausi used. * * for HP82341, the io-mapped card, we are hoping that 9914 registers are * right at base_io, but pnpdump reports that the card wants 32 addresses, * and NOT just the 8 of the 9914 registers. * * This is what I know for sure, see * http://ftp.agilent.com/pub/mpusup/pc/iop/iop_hpib.html * * - HP27209 and its minor upgrade HP82335 were memory-mapped ISA * - HP8234X series were designed to use SICL and VISA and were NOT * compatible with 82335. All were 16-bit I/O mapped ISA (not EISA) cards. * - 82340 - streamed and polled operation * - 82341A - same, and also on-board 4 KB RAM to provide buffered I/O * had an on-board PLA, allowed reconfiguration in the field * - 82341B/C - change in hardware layout, no PLA, same functionality as A * (clarification 05.2005: no FIELD-CONFIGURABLE PLA, according * to a conversation with an HP engineer in 2002; however Xilinx * chips are still on those boards ??) * - 82341D - same, but ISA PnP added * - 82350 - same, but PCI * Greg Goebel, the author of this information, has left HP in 1999 and * further or updated information is not likely to be available, ever. * * Thus, we should expect a 4k RAM somewhere on the 8234X card, but it is * NOT memory-mapped but i/o mapped. So the RAM is a fifo? * * Ed Sternin, May 2002 ***********************************************************************/ /* Readable registers of TMS9914 */ typedef struct { unsigned char *ISR0; /* Interrupt Status Register 0 */ unsigned char *ISR1; /* Interrupt Status 1 Register */ unsigned char *ADSR; /* Address Status Register */ unsigned char *BSR; /* Bus Status Register */ unsigned char *HPIBSR; /* HPIB-status */ unsigned char *UNUSEDR; /* not used for reading */ unsigned char *CPTR; /* Command Pass Through Register */ unsigned char *DIR; /* Data In Register */ } TMS9914_Registers; /* Writable registers of TMS 9914 */ #define IMR0 ISR0 /* Interrupt Mask Register 0 */ #define IMR1 ISR1 /* Interrupt Mask Register 1 */ /* Reg0+2 not used in write mode */ #define AUXCR BSR /* Auxillary Command Register */ #define ADR HPIBSR /* Address Register */ #define SPMR UNUSEDR; /* Serial Poll Mode Register */ #define PPMR CPTR /* Parallel Poll Mode Register */ #define CDOR DIR /* Command/Data Out register */ /* * typedef struct { * unsigned char *IMR0; * unsigned char *IMR1; * unsigned char *dont_use; * unsigned char *AUXCR; * unsigned char *ADR; * unsigned char *SPMR; * unsigned char *PPMR; * unsigned char *CDOR; * } TMS9914_Write_Registers; */ /* Names for the bits in the readable registers */ /* ISR0 - Interrupt STATUS Register 0 */ #define ISR0_MAC ( 1 << 0 ) /* My Address Change */ #define ISR0_RLC ( 1 << 1 ) /* Remote/Local Change */ #define ISR0_SPAS ( 1 << 2 ) /* Device has been serial polled */ #define ISR0_END ( 1 << 3 ) /* Last byte in string received */ #define ISR0_BO ( 1 << 4 ) /* Byte Out */ #define ISR0_BI ( 1 << 5 ) /* Byte In */ #define ISR0_INT1 ( 1 << 6 ) /* Interrupt status register 1 */ #define ISR0_INT0 ( 1 << 7 ) /* Interrupt status register 0 */ /* ISR1 - Interrupt STATUS Register 1 */ #define ISR1_IFC ( 1 << 0 ) /* Interface Clear */ #define ISR1_SRQ ( 1 << 1 ) /* Service Request */ #define ISR1_MA ( 1 << 2 ) /* My Address */ #define ISR1_DCAS ( 1 << 3 ) /* Device Clear Active State */ #define ISR1_APT ( 1 << 4 ) /* Address Pass Through */ #define ISR1_UNC ( 1 << 5 ) /* Unrecognized Command */ #define ISR1_ERR ( 1 << 6 ) /* Error */ #define ISR1_GET ( 1 << 7 ) /* Group Execute Trigger */ /* ADSR - Address Status Register */ #define ADSR_ulpa ( 1 << 0 ) /* LSB last address */ #define ADSR_TADS ( 1 << 1 ) /* Addressed to Talk */ #define ADSR_LADS ( 1 << 2 ) /* Addressed to Listen */ #define ADSR_TPAS ( 1 << 3 ) /* Talker Primary Addressed State */ #define ADSR_LPAS ( 1 << 4 ) /* Listener Primary Addressed State */ #define ADSR_ATN ( 1 << 5 ) /* Attention */ #define ADSR_LLO ( 1 << 6 ) /* Local Lockout */ #define ADSR_REM ( 1 << 7 ) /* Remote State */ /* BSR - Bus Status Register */ #define BSR_REN ( 1 << 0 ) #define BSR_IFC ( 1 << 1 ) #define BSR_SRQ ( 1 << 2 ) #define BSR_EOI ( 1 << 3 ) #define BSR_NRFD ( 1 << 4 ) #define BSR_NDAC ( 1 << 5 ) #define BSR_DAV ( 1 << 6 ) #define BSR_ATN ( 1 << 7 ) /* Names for the bits in the writable registers */ /* IMR0 - Interrupt MASK Register 0 */ #define IMR0_MAC_IE ( 1 << 0 ) /* My Address Change */ #define IMR0_RLC_IE ( 1 << 1 ) /* Remote/Local Change */ #define IMR0_SPAS_IE ( 1 << 2 ) /* Device has been serial polled */ #define IMR0_END_IE ( 1 << 3 ) /* Last byte in string received */ #define IMR0_BO_IE ( 1 << 4 ) /* Byte Out */ #define IMR0_BI_IE ( 1 << 5 ) /* Byte In */ #define IMR0_DMAI ( 1 << 6 ) /* xx - NOT USED on write */ #define IMR0_DMAO ( 1 << 7 ) /* xx - NOT USED on write */ /* IMR1 - Interrupt MASK Register 1 */ #define IMR1_IFC_IE ( 1 << 0 ) /* Interface Clear */ #define IMR1_SRQ_IE ( 1 << 1 ) /* Service Request */ #define IMR1_MA_IE ( 1 << 2 ) /* My Address */ #define IMR1_DCAS_IE ( 1 << 3 ) /* Device Clear Active State */ #define IMR1_APT_IE ( 1 << 4 ) /* Address Pass Through */ #define IMR1_UNC_IE ( 1 << 5 ) /* Unrecognized Command */ #define IMR1_ERR_IE ( 1 << 6 ) /* Error */ #define IMR1_GET_IE ( 1 << 7 ) /* Group Execute Trigger */ /* ADR - Address Register */ #define ADR_MASK 0x1f /* low 5 bits = primary address */ #define ADR_DAT ( 1 << 5 ) /* disable talker function */ #define ADR_DAL ( 1 << 6 ) /* disable listener function */ #define ADR_EDPA ( 1 << 7 ) /* enable dual-primary addressing mode */ /* SPMR - Serial Poll Mask Register */ /* bits 0-5, bit 7 = device status */ #define SPMR_RSV1 ( 1 << 6 ) /* Request Service bit 1 */ /* AUX - Auxiliary Command register */ /* bits 0-4 = Auxiliary command select */ /* bits 5,6 UNUSED */ #define AUX_CS ( 1 << 7 ) /* Clear/Set bit */ /* TMS 9914 Auxiliary Commands */ /* v --- C/S NA Code ? */ #define AUX_DACR 0x01 /* Release DAC holdoff */ #define AUX_DAI 0x13 /* Disable All Interrupts */ #define AUX_FEOI 0x08 /* Y Force(Send) EOI with next byte */ #define AUX_FGET 0x06 /* Force Group Execute Trigger */ #define AUX_GTS 0x0B /* Y GoTo Standby */ #define AUX_HLDA 0x03 /* Holdoff on all data */ #define AUX_HLDE 0x04 /* Holdoff on EOI only */ #define AUX_LON 0x09 /* Listen only */ #define AUX_NBAF 0x05 /* Y New Byte Availaible False */ #define AUX_PTS 0x14 /* Y Pass Through Next Secondary */ #define AUX_RHDF 0x02 /* Y Release RFD holdoff */ #define AUX_RLC 0x12 /* Y Release Control */ #define AUX_RPP 0x0E /* Request Parallel Poll */ #define AUX_RQC 0x11 /* Y Request Control */ #define AUX_RSV2 0x18 /* Request Service Bit 2 */ #define AUX_RTL 0x07 /* Return to Local */ #define AUX_SHDW 0x16 /* shadow handshake */ #define AUX_SIC 0x0F /* send interface clear */ #define AUX_SRE 0x10 /* send remote enable */ #define AUX_STD1 0x15 /* Short T1 settling time */ #define AUX_TCA 0x0C /* Y take control asynchronously */ #define AUX_TCS 0x0D /* Y take " synchronously */ #define AUX_TON 0x0A /* Talk Only */ #define AUX_VSTD1 0x17 /* Very Short T1 delay */ /** additional 'AUX' commands combined with the Set bit **/ #define AUX_SIFC (AUX_SIC | AUX_CS) #define AUX_CIFC (AUX_SIC ) #define AUX_SREN (AUX_SRE | AUX_CS) #define AUX_CREN (AUX_SRE ) #define AUX_FH (AUX_RHDF)